Synchronized pulsed lada for the simultaneous acquisition of timing diagrams and laser-induced upsets

ABSTRACT

Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application claims priority benefit from U.S. Provisional Application No. 61/804,696, filed on Mar. 24, 2013; from U.S. Provisional Application No. 61/806,803, filed on Mar. 29, 2013; and from U.S. Provisional Application No. 61/838,679, filed on Jun. 24, 2013; the disclosures of which are incorporated herein by reference in their entirety.

GOVERNMENT LICENSE RIGHTS

This invention is based upon work supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Project Activity (IARPA), via Air Force Research Laboratory (AFRL) contract number FA8650-11-C-7104. The ideas and conclusions contained herein are those of the inventors and should not be interpreted as necessarily having the official endorsements, either expressed or implied, of ODNI, IARPA, AFRL, or the U.S. Government.

BACKGROUND 1. Field of Invention

This invention is in the field of laser-based defect localization analysis of integrated circuits (IC). More specifically, this invention is about design debug and/or failure analysis of ICs using the laser assisted device alteration (LADA) technique.

2. Related Art

LADA (Laser-Assisted Device Alteration) is a technique that depends on the ability of a continuous-wave (CW) laser to generate localized photocurrents in an integrated circuit through its backside and thus change the pass/fail outcome of a test stimulus on a “sensitive” transistor, thereby localizing sensitive areas including design or process defects. The laser is used to temporarily alter the operating characteristics of transistors on the device. The current spatial resolution using the 1064 nm continuous wave laser is 240 nm.

An explanation of the LADA techniques can be found in, for example, Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA), Jeremy A. Rowlette and Travis M. Eiles, International Test Conference, IEEE Paper 10.4, pp. 264-273, 2003. That paper described the possibility of using a CW laser of 1064 nm or 1340 nm wavelength. It is explained that the 1340 nm would cause device alteration via localized heating, while the 1064 nm would cause device alteration via photocurrent generation. It is also noted that the 1064 nm laser has a spatial resolution advantage. Therefore, the authors recommend the use of 1064 nm laser.

As shown in FIG. 1, conventional LADA uses a CW laser to induce electron-hole pairs in the device under test from the backside. The electron-hole pairs so generated affect the timing of the nearby transistor—thus facilitating critical path analysis. A DUT 110 is coupled to a tester 115, e.g., a conventional Automated Testing Equipment (ATE), which is connected to computer 150. The ATE is used in a conventional manner to stimulate the DUT with test vectors and study the response of the DUT to the test vectors. The ATE can be replaced by a system test board, optionally controlled by a PC or such. Therefore, sometimes reference will be made to Testing Equipment (TE) as shorthand for either an ATE or other means for testing the DUT. Conversely, all references to ATE incorporate the use of other testing means as well. The response of the DUT to the test vectors can be further investigated using the LADA. For example, if the DUT fails a certain test, LADA can be used to investigate whether the DUT can pass under certain conditions and, if so, which device, i.e., transistor, was responsible for the failure. Conversely, when the DUT passes certain tests, LADA can be used to investigate under which conditions the DUT will fail these tests and, if so, which device, i.e., transistor, was responsible for the failure.

The LADA system for FIG. 1 operates as follows. Tiltable mirrors 130 and 135 and objective lens 140 are used to focus and scan a beam from CW laser 120 onto the DUT 110. This allows the laser 120 to generate photo carriers in the silicon of the. The electron-hole pairs so generated affect the timing of the nearby transistor, i.e., decreasing or increasing transistor switching time. The tester is configured to place the operating point of the device under test in a marginal state by applying a recurrent test loop of selected voltage and frequency. The laser stimulation is then used to change the outcome of the tester's pass/fail status. The beam's location at each point is correlated to the pass/fail outcome of the tester, so that when a change is detected, i.e., a previously passing transistor is now failing or vice versa, the coordinates of the laser beam at that time points to the location of the “borderline” transistor.

During the LADA analysis, the tester (ATE) is configured to place the operating point of the device under test in a marginal state. The laser stimulation is used to change the outcome of the tester's pass/fail status. The present state-of-the-art in laser assisted fault spatial localization is about 240 nm resolution. The limitation on further improvement of the single photon LADA spatial resolution is imposed by the laser light wavelength. As noted in the Rowlette paper, the spatial resolution is enhanced by using shorter wavelength. However, optical absorption of silicon at wavelength smaller than 1064 nm prevents the use of shorter wavelengths, as it becomes the major obstacle for delivering light to the transistor through the backside. Thus, while design rules of modern devices shrink, the spatial resolution of the LADA system cannot be improved by the use of smaller wavelength laser. For example, at 22 nm design rule it is doubtful that conventional LADA will be able to resolve among four neighboring transistors.

Optical beam induced current (OBIC) is another test and debug analysis technique in which laser beam is illuminating the DUT. However, unlike LADA, OBIC is a static test, meaning no stimulus signal is applied to the DUT. Instead, the laser beam is used to induce current in the DUT, which is then measured using low-noise, high-gain voltage or current amplifiers. OBIC has been used in a single-photon mode and in a two-photon absorption mode, sometimes referred to as TOBIC or 2P-OBIC (two-photon optical beam induced current).

Two-photon absorption (TPA) is the simultaneous absorption of two photons of identical or different frequencies in order to excite a molecule from one state (usually the ground state) to a higher energy electronic state. The wavelength is chosen such that the sum of the photon energy of two photons arriving at the same time is equal to the energy difference between the involved lower and upper states of the molecule. Two-photon absorption is a second-order process, several orders of magnitude weaker than linear (single-photon) absorption. It differs from linear absorption in that the strength of absorption depends on the square of the light intensity, thus it is a nonlinear optical process.

SUMMARY

The following summary of the disclosure is included in order to provide a basic understanding of some aspects and features of the invention. This summary is not an extensive overview of the invention and as such it is not intended to particularly identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented below.

Various embodiments disclosed enable higher spatial resolution of fault localization by utilizing time domain to enable enhanced spatial resolution. Disclosed embodiments utilize a pulsed laser with sufficient energy in lieu of a continuous wave laser. The pulsed laser is synchronized to the device's clock, thus enabling improved spatial resolution. Various embodiments utilize a 1064 nm wavelength laser for a single-photon LADA, or longer wavelengths so as to exploit the non-linear two-photon absorption mechanism to induce LADA effects. This later technique is referred to herein as Two-Photon Laser Assisted Device Alteration technique (2pLADA).

Disclosed embodiments enable fault localization by using test vectors stimulating a DUT and at the same time use a femtosecond, a pico-second, or even a nano-second pulsed laser to scan an area of interest in the DUT and examine the response of the DUT to the test vectors during the scan. The laser source is chosen such that the wavelength provides photon energy below the band gap of silicon and it provides pulses of femtosecond pulse width. The pulse widths for optimum resolution relates to device operating frequency. A clock signal is obtained from the ATE and is fed to the DUT and to the circuit controlling the pulsed laser. The timing of the pulses can be shifted relative to the ATE clock, so as to investigate the pass/fail characteristics of various devices. Additionally, by using proper synchronization of the laser pulses to the clock, spatial resolution is enhanced to enable resolving multiple devices, i.e., transistors, within the laser beam.

Furthermore, according to disclosed embodiments, the laser beam is consecutively parked so as to illuminate selected areas of the DUT, and LADA data is collected for each location. Also, for each location, the timing of the laser pulse arrival is varied with respect to the clock signal. Then, for each location, a plot is constructed from the collected LADA data, so as to study the device's behavior over time, i.e., the device response to the arrival time of the laser pulse with respect to the test vector.

According to further aspects, the LADA testing is used to study single-event upset generation inside the DUT.

Various embodiments provide a laser assisted device alteration (LADA) system operable in conjunction with an automated testing equipment (ATE) for testing integrated circuit device under test (DUT), comprising: timing electronics receiving a clock signal from the ATE, the timing electronics generating a synch signal for synchronization of laser pulses to the clock signal; a pulsed laser source generating the laser pulses; optical arrangement receiving laser pulses from the tunable pulsed laser source and directing the laser pulses onto desired locations on the DUT; a controller configured to operate the timing electronics for timing the laser pulses to arrive at transistors in the DUT at times synchronized to the clock time and enable incorporating a delay or advance of the laser pulses with respect to the clock time, to thereby alter the transistors electrical response to test signals applied to the DUT from the ATE, a single-pixel sensor detecting reflections of the laser pulses from the DUT and generating corresponding intensity signals, and wherein the controller is configured to detect the altered transistors electrical response, receive the corresponding intensity signals, and utilize the electrical response and intensity signals to generate a plot of electrical response versus time for a selected location on the DUT.

According to aspects of the invention, a method to extract individual timing diagrams and flip-flop upset mapping from synchronized single- or two-photon pulsed LADA is enabled by spatially positioning, or “parking”, the incident laser beam on a circuit feature of interest, then temporally scanning the arrival time of the laser pulses with respect to the tester clock or the loop length trigger signal, and then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. The method may include an analysis of two-photon-induced upset sites to provide flip-flop transistor upset mapping and logic state manipulation and display with CAD overlay for circuit analysis and image registration. The realization of non-destructive, two-photon-absorption-induced upset sites is acquired through a LADA-based implementation scheme enabling an alternative to single-event upset execution and evaluation.

According to another aspect, a method to acquire multiple timing diagrams simultaneously is provided by capturing LADA activity from multiple structures within a confined region of interest in a LADA image as the laser pulse arrival time is temporally scanned with respect to the tester clock or the loop length trigger signal; and extracting the temporal evolution of transistor switching events (i.e. timing diagrams).

According to yet another aspect, a method is provided to extract synchronized single- or two-photon pulsed LADA-based timing diagrams over an extrapolated physical area located across the DUT to facilitate the automatic spatiotemporal interrogation of LADA activation sites through a server-controlled CAD and circuit schematic management facility, the process flow comprising:

a. previewing CW LADA activations sites in a controlled spatial area of interest; b. registering specific activation sites for CAD overlay; c. selecting associated cell blocks or a larger physical area; d. constructing the logic path between LADA activations sites; e. interrogating the area of interest using synchronized single- or two-photon pulsed LADA; f. extracting the associated timing diagrams; g. extracting related circuit schematics of related nets; h. locating the subsequent LADA site in the sequence; and, i. repeating the steps e-h until interrogation of the entire race is completed.

According to further aspects a method is provided to visualizing failure rate of transistors in a DUT, comprising the steps of receiving pass and fail data from a tester; receiving location information indicated a location on the DUT where a charge injector injects charges; configuring pixels of a monitor display according to the location on the DUT; storing each pass result as a first pixel color in the display; storing each fail result as a second pixel color in the display; and repeating the scanning of the display to aggregate/average the outcomes of repeating the test pattern and the charge injections for each pixel corresponding to an area of interest in the DUT. In a grey scale display, the first color can be white while the second color is black.

In an embodiment, a display integrates both pass results and fail results to effectively present a shade of grey by a time series of black and white spots. The repetition of pixel dwell time at a particular spatial location, the decay of a phosphor, or the after image on the retina effectively averages pass data and fail data to provide a color in the range of grey scale. When running the test patterns during photon injection, the earliest indication that an area is of interest is emerging when artifacts emerge from the background grey comprising 50% black and 50% white. While this observation may be captured photographically, storing data to non-transitory media would allow further analysis by location in correlation to a schematic or layout of the DUT. An accumulator circuit that stores positive and negative values would provide a non-zero count of test results for a block of pixels. Then zooming into that block may provide sufficient resolution to a junction or analysis of the patterns could reveal which junctions had transitions during the sensitive time segment.

Other aspects and features of the invention would be apparent from the detailed description, which is made with reference to the following drawings. It should be appreciated that the detailed description and the drawings provides various non-limiting examples of various embodiments of the invention, which is defined by the appended claims.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, exemplify the embodiments of the present invention and, together with the description, serve to explain and illustrate principles of the invention. The drawings are intended to illustrate major features of the exemplary embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of actual embodiments nor relative dimensions of the depicted elements, and are not drawn to scale.

FIG. 1 illustrates a prior art CW LADA system.

FIG. 2 illustrates an embodiment of pulsed-laser LADA system.

FIG. 2A illustrates an embodiment of the two feedback loops.

FIG. 2B illustrates an embodiment using a fixed-pulsed laser source to generate clock signal.

FIG. 3 illustrates an embodiment to achieve a synchronization scheme.

FIGS. 4A-4C illustrate how pulsed laser LADA helps individually identify and isolate both the P- and NMOS transistor locations in close proximity.

FIGS. 5A-5D illustrate enhanced spatial resolution as a consequence of accurate pulse placement capabilities.

FIG. 6 illustrates an embodiment of laser repetition rate locking scheme.

FIGS. 7A-7C illustrate steps taken to measure minority carrier lifetime using LADA, according to one embodiment.

FIG. 8 illustrates an embodiment of pulsed-laser LADA system, while FIG. 8A illustrates plots made using the system of FIG. 8 and FIG. 8B illustrates the progression of image development and plot construction over time.

FIG. 9 illustrates an embodiment of an architecture of a pulsed-laser LADA system that can be used for the system illustrated in FIG. 8.

DETAILED DESCRIPTION

FIG. 2 illustrates an embodiment which uses a pulsed laser source with sufficient energy in lieu of a continuous wave laser. This embodiment concerns applying photon absorption to precisely inject carriers into an IC for the purposes of fault localization using the LADA technique and can be used for IC characterization and finding ways to improve the design. The technique is based on photons arriving at a focus in the transistor so that the delivered photon energy is greater than what is needed for electron hole pair creation (>1.1 eV in silicon, for example; other ICs such as GaAs, SiGe, InP, etc, have different bandgap energies). Photon stimulation in this embodiment requires excitation with laser pulses in the range of nanoseconds to femtoseconds. The signal is localized to the focal spot of the laser, providing an immediate improvement in fault localization. The effective volume in which the electron-hole pair generation occurs seems to be reduced due to the synchronization. The embodiments use sophisticated timing electronics to precisely control the timing of the laser pulse with respect to the transition of an edge of the tester clock, e.g., ATE clock. This type of control allows to finely vary the delay or advance of signals propagating through the transistor of interest for LADA.

FIG. 2 illustrates an embodiment of the invention, wherein a DUT 210 is coupled to an ATE 215, as in the prior art. However, in the embodiment of FIG. 2, nanosecond to femtosecond laser pulses are generated by pulsed laser source 225, which are then focused onto the DUT 210 using tiltable mirrors 230 and 235 and objective lens 240. For 2pLADA the laser source 225 provides a pulsed laser beam of wavelength that is longer than the silicon bandgap, i.e., longer than 1107 nm. In one embodiment wavelength of 1550 nm is used, while in another 1340 nm or 1250 nm are used. On the other hand, the same arrangement can also be used for single-photon LADA, in which case the laser source can provide pulsed beam of wavelength such as 1064 nm. In this embodiment, the tiltable mirrors 230 and 235 are implemented as a laser scanning microscope (LSM). Also, in some embodiments a solid immersion lens (SIL) is used as part of the objective lens arrangement 240.

In conventional LADA systems the laser is always on; however, according to embodiments of the invention, very short pulses are used. Therefore, it is important that the device transition occurs when the laser pulse arrives at the device. To achieve that, a trigger signal 245 is obtained from the ATE and input to timing electronics 260, which controls the pulsed laser 225 to synchronize the laser pulses with the test signals of the ATE.

Using the system shown in FIG. 2, first the tester (ATE) 215 is operated to apply a set of test vectors to determine the marginal settings of the DUT 210. That is, the voltage and frequency of the test vectors are varied to determine the point where the DUT is just about to fail, or has just failed the test, e.g., the DUT is failing the test 50% of the times of a test loop. This is the DUT's pass/fail boundary condition. The voltage and frequency settings are then used to generate a repetitive test signal to repeatedly stimulate the DUT at its pass/fail boundary condition.

As the DUT is stimulated at the boundary condition, a sync signal 245 is sent from the tester 215 to the timing electronics 260. The timing electronics 260 controls the laser source 225 to obtain laser pulses of picosecond to femtosecond pulse width and of wavelength higher than silicon band gap for 2pLADA or shorter for single-photon LADA. In general, for 2pLADA the wavelength is about 1250 nm to 1550 nm and the pulse width is about 100 fs. For single-photon LADA the wavelength may be 1064 nm and the pulse width can be in the nanosecond or femtosecond range. The laser pulses are scanned over an area of interest in the DUT 240 to thereby increase or decrease the DUT's switching time and push the DUT beyond the boundary condition. That is, if the voltage/frequency of the test vector are set such that the DUT is just about to fail, the laser pulses are timed to cause the DUT to fail. Conversely, if the voltage/frequency of the test vector are set such that the DUT is just failing, the laser pulses are timed to cause the DUT to pass the test. During this time the output of the DUT is monitored to determine location of the failure. That is, at the moment in time where the output signal from the DUT indicates a failure (where without the laser beam the DUT would pass), the location of the beam over the DUT is determined, to thereby determine the location of the transistor causing the failure. Conversely, at the moment in time where the output signal from the DUT indicates a pass (where without the laser beam the DUT would fail), the location of the beam over the DUT is determined, to thereby determine the location of the transistor previously causing the failure and now passing.

It should be appreciated that since a sync signal is obtained from the tester, the timing of the laser pulses can be varied so as to vary the amount of the photo-generation (single-photon or two-photon) effect on the transistor. That is, the timing of the laser pulses can be varied so as to increase or decrease the amount of increase or decrease the DUT's switching time. This ability can assist in determining the severity of the fault, in addition to its location.

Embodiments of the invention also use timing electronics to precisely control the timing of the laser pulse with respect to the transition of an edge of the tester (e.g., ATE) clock. This type of control allows to finely vary the delay or advance of signals propagating through the transistor of interest. In one example, two phase locked loops (PLL) are used to precisely control the pulsed laser, as illustrated in FIG. 2A. In FIG. 2A the ATE 215 provides a clock signal, Clk, and a test loop signal, Test Loop. Both clock signal and test loop signal are input to the DUT and are tapped and sent to the timing electronics 260, which forms the first PLL. The laser source 225 includes a second PLL.

That is, the PLL of the laser source 225 ensures that the pulse frequency of the laser pulses is stable and accurate to the desired frequency, e.g., 100 MHz. Conversely, the first PLL of the timing electronics provides synchronization of the frequency of the second PLL to the clock signal of the ATE. Notably, in this context, synchronization does not necessarily mean that the laser pulses and the clock pulses are concurrent, but rather that they are synchronized over a test loop period. So, for example, the timing of the laser pulses may be shifted, such that the pulses appeal at the middle of the clock signal for every clock pulse, as illustrated by pulse train 227, or at the end of each clock pulse, as shown by pulse train 229, etc. That is, the laser pulses may be delayed or advanced with respect to the clock signal of the ATE, but remain synchronized to the clock signal of the ATE.

On the other hand, as will be elaborated below, the frequency of the laser pulses may be a multiple of the ATE clock signal. For example, laser pulse train 223 has a multiplier of 7, such that seven laser pulses are generated for every one clock pulse of the ATE. Using a multiplier larger than 1, one can probe whether the failure is at the rising edge, trailing edge, etc. Also, it is not necessary to provide delay or shift of the pulses, since the plurality of laser pulses for each clock pulse serve the advance/delay function. Conversely, it is also possible to have a multiplier smaller than 1. For example, in the pulse train 224 the multiplier is ½, such that a laser pulse arrives only every other clock signal. Such an arrangement can be used to validate that the failure is indeed due to the laser pulses, since if it is due to the laser pulses, then the device would fails about 50% of the time.

FIG. 3 illustrates an embodiment to achieve a synchronization scheme. The output pulses from a pulsed laser source (1) of nano-to-femtosecond temporal duration can be synchronized to the clock cycle of an integrated circuit (IC) (2) through an intermediary phase-locked loop (PLL) circuit (3). In this configuration, the PLL circuit accepts the clock cycle frequency of the IC and locks it to an internal crystal oscillator of the same frequency. In this embodiment, the clock and crystal oscillator frequencies are fixed at 100 MHz. The IC clock signal can be generated by the ATE (not shown). This enables a 1:1 optical pulse to transistor-switching-event synchronization ratio. Under these conditions, practically speaking, these values can be fixed anywhere in the range from 1 kHz to 10 GHz, before the efficiency of the photon absorption rate becomes severally diminished.

It is noted here that optical sources faster than 1 GHz are not desirable for nonlinear studies such as with 2pLADA, since in general the peak optical power contained with each pulse is inversely proportional to the repetition rate. Therefore, high repetition rates equal low peak optical powers which results in ineffective, if any, two-photon absorption. For 1:1 synchronization ratio single-photon studies at 1064 nm on the other hand, multi-GHz optical sources may be beneficial since the optoelectronic interaction scales linearly with incident optical power. In addition, it should be noted that the efficiency of two-photon absorption is directly proportional on the incident pulse duration, where femtosecond optical pulses facilitate higher peak optical powers than a picosecond or nanosecond alternative and therefore providing improved nonlinear absorption. As a result, it is desirable for nonlinear studies to utilize ultrafast (i.e. picosecond or femtosecond) optical pulses. On the other hand, for single-photon studies, the pulse duration is not a limiting parameter with regard to absorption rate and so does not restrict performance. If anything, it enables an additional probing parameter (e.g. for measuring optical pulse interaction periods vs. photoelectric device stimulation). Furthermore, the silicon absorption coefficient is greater for single-photon wavelengths <1130 nm compared to two-photon-absorption-tuned wavelengths (i.e. □□≥1250 nm).

In order to maintain the efficiency, one can modify the synchronization scheme in order to match integer multiples of incident optical pulses to transistor switching events (or device clock frequencies). For this to succeed, the laser source must be designed to produce a higher than 1 GHz repetition rate and have a scalable pulse picker module in place, post pulse optimization, in order to amend the synchronization ratios. For example, instead of matching each incident optical pulse to every transistor switching event, one could match every second pulse to every subsequent switching event; thus, creating a 2:1 synchronization ratio. Practically, this would translate into the use of a 200 MHz repetition rate laser and a 100 MHz device frequency, or a 1 GHz repetition rate laser and a 500 MHz device frequency, and so on. Alternatively, one could tune the ratio to be 3:1 or 4:1, etc., so long as the ratio corresponds to an optoelectronic overlap with the clock pulse in synchronization with the test loop signal. Under this synchronization scheme, the efficiency of photon absorption is not decreased; however, the rate at which absorption takes place does, generating a photon signal intensity that is negatively scaled as per the synchronization ratio. It must be noted here that this may not be a limiting factor for laser-induced studies of integrated-circuits. For each device under test, there is a requirement to perform a photon scalability calibration in order to determine the maximum synchronization ratio allowed. Furthermore, by integrating a tunable optical source (i.e. 1000-1600 nm output wavelength) into such a system, one can interchange between single-photon and two-photon absorption regimes since two-photon absorption begins to dominate over single-photon absorption at wavelengths larger than about 1200 nm in silicon.

Once these frequencies (i.e. the clock and crystal oscillator frequencies) are locked together, the PLL circuit output signal is then sent through a 100 MHz (or clock frequency) electronic filter to the pulsed laser to serve as its input stimulus. The benefit here is that the PLL circuit has full control over the phase of its output signal. Therefore, one can control the repetition rate, and hence the pulse arrival time, of the laser's optical output. This can be verified by comparing the output clock frequency from the IC to the trigger output from the pulsed source on an oscilloscope (9). In this example the PLL circuit can electronically accommodate phase delays of about 600 fs; however, due to the board's electrical jitter, a minimum phase delay is set to about 20 ps. The system's electrical jitter is directly proportional to the accuracy at which the optical pulses can be positioned relative to the switching time of the individual transistors under evaluation. Therefore, since the system's electrical jitter is 20 ps, the optical placement accuracy is also 20 ps—there is a one-to-one correspondence. This is a crucial parameter since it can negate the timing benefits to be gleaned if the electronic placement error is larger, for instance, than the 2pLADA femtosecond pulse duration. Femtosecond optical pulses increase the local energy density as required for efficient two-photon absorption; however, when the electrical jitter eclipses this isolated carrier generation timescale then the jitter can limit the subsequent signal generation and temporal precision of the now time-resolved data.

The laser pulses are then coupled into a laser scanning microscope (LSM) (4) where they can be accurately distributed across a particular location on the IC. The LSM is controlled using a computer (6) which hosts a graphical user interface as well as a custom digital signal processor (DSP) suite. In disclosed embodiments, this applications suite gives the end user, through a preconfigured DSP circuit (7), the ability to directly communicate with the PLL circuit which in turn provides full control over the laser pulse's arrival time at the device, e.g., by delaying or advancing the pulses.

With regard to the device 2, it can be electrically stimulated to produce preconditioned LADA pass/fail values through the use of a custom applications interface (5). This board compares a real-time acquisition value from a counter, latch and shift register arrangement against a loaded reference value which was inserted beforehand by selecting a reset switch. Fine control over the real-time loaded counter value can be controlled through an analog fine delay potentiometer on the applications interface board which alters the timing of the latch enable function on the IC. This configuration allows the user to condition predominantly passing, failing or balanced comparator output values. These pass/fail output values are then sent to a data conditioning circuit (in this example, a field-programmable gate array FPGA 8) which is programmed to accept a real-time digital pass/fail stimulus, conditioned to scale between failing values from 0-100%, and delivers an averaged (about 40 us period) digital output, again scaled between 0-100% fail, for enhanced visualization and biasing of the resulting pass/fail levels in the graphical user interface. The data conditioning circuit can also be used in conjunction with the applications interface board in order to calculate the magnitude of laser-induced timing delays by calibrating the application board's output delay voltage.

In the embodiments described above, a tunable pulsed laser source is used, and the pulse frequency is tuned so as to synchronize to the ATE clock. While these embodiments are operable, a tuned pulsed laser source is rather expensive and requires the phase locked loop described above. FIG. 2B illustrates another embodiment, which enables LADA testing using a simpler fixed pulsed laser 255. For example, a mode-locked laser source can be used. Mode-locking is a technique in optics by which a laser can be made to produce pulses of light of extremely short duration, on the order of picoseconds or femtoseconds. The laser pulses are used as the clock, which is fed to the timing electronics 265. Conventional ATE's have clock input port and are programmable to use the input clock in order to generate the clock, Clk, and the test loop signals for the DUT. Therefore, in one example, the clock signal from the timing electronics 265 is input to the ATE, and the ATE is programmed to use that input to generate the clock and test loop signal.

However, as noted above, to obtain the most benefit of the pulsed laser LADA, it is desirable to adjust the pulses such that the laser pulses arrive at the transistor at different times during the clock cycle, e.g., leading edge, middle, trailing edge, etc. In the embodiments of FIG. 2, 2A and 3, this was done by advancing or retarding the laser pulses. However, in the embodiment of FIG. 2B the laser pulses are fixed and cannot be changed, so retarding or advancing the laser pulses is not a viable option. Therefore, according to one embodiment, the ATE is programmed to retard or advance its clock signal in synchronization with the clock signal received from the timing electronics 265. In this manner, the timing of the arrival of the laser pulses at the transistor can be tuned to leading edge, trailing edge, etc., of the ATE clock signal.

On the other hand, since in general the ATE and the LADA testers are made by different manufacturers, and the actual testing is performed by an engineer from yet a third company, it would be beneficial to simplify the operations of the testing engineer and offload the retardation or advancement of the signal from the ATE. This is done by using the phase shifter 275, illustrated in the embodiment of FIG. 2B. That is, using the phase shifter 275, the clock signal output from the timing electronics 265 can be advanced or retarded with respect to the laser pulses. The resulting modified signal is then sent to the ATE as the input clock signal. Consequently, when the ATE output its clock and test loop signals, they are both can be shifted or retarded with respect to the laser pulses.

EXAMPLES

Constructing a pulsed LADA system with a pulsed optical source allows for novel aspects of the operating device to be evaluated and measured. When traditional single-photon or alternative two-photon LADA utilize a CW laser, the optical radiation is constantly interacting with the individual transistors with a potentially damaging level of invasiveness. A pulsed LADA methodology, on the other hand, allows the switching characteristics of the individual transistors to be mapped out in as much as two-physical dimensions. Extended pulsed LADA concepts are discussed in detail below.

Under conventional CW LADA stimulation, device theory and practice informs us that the magnitude of laser-induced device perturbations from a p-type metal-oxide-semiconductor (PMOS) transistor dominates over its n-type (NMOS) neighbor. Since the diameter of the laser beam would cover both the p-type and its neighboring n-type transistors, the resulting spatial resolution is insufficient to distinguish the failing transistor. On the other hand, using the disclosed embodiments in a pulsed arrangement, temporal resolution is used to achieve higher spatial resolution, even when a larger wavelength laser is used. That is, since the incident pulses are tuned to the exact temporal switching interval of the transistors under investigation, and also because the peak power contained in each pulse is significantly higher than in CW mode, it is possible to individually identify and isolate both the P- and NMOS transistor locations in close proximity. This is impossible under CW excitation and therefore creates a new experimental avenue for semiconductor device design debug and characterization to explore, even at increasingly small design rules. This addresses a growing concern within the semiconductor device failure analysis community where optically-induced transistor recognition and operating characteristics are of critical importance as the latest technology nodes are scaled toward lower nanometer geometries. Consequently, synchronized pulsed LADA offers more value than its CW counterpart.

A schematic example of such improvements is presented in FIGS. 4A-4C. In continuous-wave mode, the PMOS signal generally dominates, resulting in a generalized spatial distribution of a single signal, as illustrated in FIG. 4A. It is incredibly difficult here to discern individual physical transistor distributions and/or match these LADA manifestations to computer-aided design (CAD) layouts. Theoretically, each transistor should generate its own LADA signal—no matter the magnitude of the laser-induced effect, as illustrated in FIG. 4B. These would perfectly trace out the physical location of the individual transistors allowing for rapid physical and/or optoelectronic recognition. This can be replicated in the pulsed domain using the embodiments discussed above. That is, the laser pulses are timed and synchronized to the test signal, such that they arrive at the P- and NMOS transistor locations according to the user's selection. The pulses can be timed to the switching of the PMOS transistors to test them, or to the switching of the NMOS to test the NMOS transistors, as illustrated in FIG. 4C. Therefore, unique transistor switching evaluations as well as CAD-enhanced physical mapping/recognition of LADA signals can be performed, regardless of the spatial laser coverage.

Furthermore, an additional benefit of the increased peak power from ultrafast pulses (aside from the ability to generate LADA signals more efficiently, i.e., acquiring fewer image averages) is the generalized increase/decrease (depending on whether you perturb a P- or N-MOS transistors) in laser-induced critical timing path perturbations and therefore improved LADA signal collection. Larger incident optical power increases the number of photo-injected carriers within the silicon, which in turn enhances the probability of stimulating optoelectronic fluctuations within the device structures. This leads to superior LADA signal responses which can be more readily measured with a reduced level of invasiveness—pulsed optical sources are actually off for longer than they are on, limiting the opportunity for thermal build up and damage. For example, an ultrafast laser with a pulse duration of 10 ps and a repetition rate of 100 MHz is off for a duration of 10 ns—creating a ratio of 1:1000 (ON:OFF)—thereby providing ample cooling off period. However, it should be noted that it is ultimately the power ratio that causes the heating. For example, a single optical pulse containing 1 kJ of incident optical energy would satisfy the above criteria however it also contains enough energy to potentially permanently damage the device through some other thermal or non-thermal optoelectronic mechanisms.

Also, with the facility to noninvasively inject significant levels of optical power into a specific transistor comes the opportunity to disturb previously overlooked transistor locations. Naturally, a greater level of photo-carrier generation within the vicinity of a given region of interest (which is populated with transistors of varying sensitivity) increases the probability of visualizing a wider range of LADA manifestation sites. These activation regions can be stimulated with approximately 10-100 uA of laser-induced photocurrent; however, with an ultrafast laser pulse boasting peak optical powers approaching 10-100 kW it may be possible to inject 10-100 mA of photocurrent (while maintaining a safe level of invasiveness) within the device which may be enough to perturb ‘healthy’ transistors.

Efficient two-photon absorption can be obtained in silicon with a focal laser power density of more than 10 MW/cm² (Megawatt/centimeter squared); however, single-photon values will be approximately 106 times smaller due to its relative absorption cross-section. The level of incident optical power (or local power density) required for efficient, non-invasive photo-carrier injection will decrease as the spatial geometries of the transistors under evaluation also decrease. Also the generation of two-photon absorption is not dependent on a specific power density threshold—two-photon absorption is an instantaneous, quantum mechanically defined, nonlinear process which is sensitive to the imaginary part of the third-order nonlinear susceptibility (i.e. it exhibits an intensity-squared dependence, not a power density dependence).

Even though a two-photon wavelength of 1250 nm generates effectively 625 nm inside the silicon (where the absorption cross-section is higher than 1064 nm), the intensity-dependent nature of the absorption process reduces its overall relative rate of absorption. Two-photon absorption is directly proportional to the square of the incident optical intensity. In addition, silicon doping levels also contribute to this discussion—i.e. increased or decreased doping concentrations affect the level of absorbance as a function of wavelength. This single-photon-biased opportunity however enables another novel laser-probing and device characterization platform for enhanced critical timing analysis of racing/switching signal levels within transistors. CW LADA cannot offer this type of interrogation due to limitations from invasiveness (i.e. the laser—is always on) and limited power delivery capabilities. Time-resolved pulsed probing, on the other hand, may allow failure analysts to investigate, for the first time, transistor switching physics on healthy, design-defined nodes as well as the subsequent down-chain device performance/interactions also. In order to effectively implement this type of device characterization, an understanding of the level of incident optical power required plays an important role. Perturbing ‘healthy’ transistors requires high peak powers while facilitating a minimal level of invasiveness. With that said, optimization of the temporal duration of the incident optical pulses is required. Clearly, picosecond pulse durations at 1064 nm provide significant levels of incident optical power (hence, photo-carrier generation) at the transistor level since, for example, a 10 ps laser pulse at a repetition rate of 100 MHz and an average power of 4 mW generates a peak power of 4 W; however, this may be limited if the laser repetition rate is matched to a faster than 1 GHz clock frequency from a device under test. Increasing repetition rates results in decreasing peak powers. Therefore, a more suitable alternative is the use of a femtosecond laser source. The laser repetition rate could be scaled in accordance with the device operation frequency while providing enhanced levels of peak optical power since the pulse duration has reduced by a factor of 1000—increasing the peak power by the same magnitude (4 kW in the example given above). An additional benefit of the femtosecond pulse duration would be the improvements in temporal characterization; however, this is restricted by the magnitude of the synchronization scheme's electrical jitter—as described previously. Finally, femtosecond laser pulses provide a reduced level of optical invasiveness compared to picosecond or nano-second pulses, minimizing the potential for laser-induced damage to the device.

In addition, a pulsed LADA system demonstrates enhanced spatial resolution as a consequence of accurate pulse placement capabilities. Again, when in CW mode, the laser continuously stimulates a specific region of interest while inferring LADA information in real-time. This results in a spatially averaged two-dimensional LADA image since there is no discrimination between the highly ordered sequences of circuit functionality (i.e. propagating signal paths vs. time) where a collective distribution is acquired with a PMOS dominated bias. In pulsed mode however, one can discern between these propagating speed paths with an accuracy of about 20 ps, allowing for highly confined LADA signal manifestations which have an enhanced lateral resolution since they individually and temporally address spatially separated neighboring transistors that are not configured to switch until later in the device operational cycle. This enhances the LADA isolation resolution as well as the physical LADA resolution.

A schematic example is presented in FIGS. 5A-5D. In continuous-wave mode, since the spatial distribution of LADA signals is time-averaged, the resulting two-dimensional LADA map has a generalized optoelectronic structure which may be biased according to the individual transistors' LADA signal strengths (since PMOS generally dominates over NMOS). These images, illustrated in FIG. 5A, suffer from poor spatial resolution and limited CAD overlay capabilities. In pulsed mode however, the LADA image can be enhanced and its spatial resolution improved due to the time-resolved nature of the acquisition process. By individually addressing each transistor as a function of both space and time (and with sufficient incident optical power so as to remove any PMOS biasing effects), neighboring transistor influence is effectively removed from perturbing the LADA acquisition since there is now a tester-driven, transistor-dependent sequence of events controlling the device operation. Each transistor is configured to switch in a systematic, time-dependent order, allowing for the incident optical pulse to directly manipulate and measure each transistor in two physical dimensions (i.e. X and Y) as well as time. As a result, the spatial resolution of the acquired LADA signal is improved and therefore additional, previously unobtainable, device data may be extracted, as illustrated in the sequence of FIG. 5B-5C, showing images taken at different times, each with its temporal and spatial separation.

Aside from gleaning only LADA-specific data from this technique, it is also possible to determine additional optoelectronic phenomena as well. One example would be the measurement of laser-induced carrier lifetimes. Currently, the carrier lifetime inside specific device locations is tremendously difficult to quantify since it depends on a number of different optoelectronic parameters, such as material composition, dimensions, geometries and electric-field magnitudes and directions, etc. With pulsed LADA however, one may be able to directly measure this electronic timescale through a pseudo pump-probe type technique where the creation of a transistor-specific LADA event is linked to the arrival time of a laser pulse. The measured carrier lifetime may require the consideration (i.e. subtraction) of the system's electronic response time for a more accurate representation.

When using single-photon LADA, i.e., laser pulses of wavelength 1064 nm, the magnitude of the measured LADA effect is directly proportional to the magnitude of the laser-induced photo-current (this is when using linear absorption, as the LADA signal would respond quadratically with a two-photon technique). According to one embodiment, the LADA signal is mapped out as a function of laser pulse arrival time. Then it would be possible to extract the carrier lifetime, since the lifetime will dictate the magnitude of the resulting LADA signal.

A process for accomplishing this according to one embodiment would be as follows. First, a laser beam (e.g., a CW laser beam of wavelength 1064 nm) is parked to illuminate a sensitive transistor, so as to obtain an optimum LADA signal. This is illustrated in FIG. 7A. The spatial coordinates of the laser beam at the optimum LADA signal indicates the proper spatial coordinates of the transistor. Then the CW laser source is disabled and the pulsed laser source is activated and the laser pulses are directed to the same spatial coordinates obtained from the CW laser. The laser pulse timing is adjusted to obtain and measure the optimum LADA signal, so as to obtain the proper temporal overlap with the tester (e.g., ATE) pulses arriving at the transistor. This is illustrated in FIG. 7B. At this time, the optimized the spatial overlap of the laser spot with the transistor and the temporal overlap of the laser pulses with the test signal have been achieved. Then, the laser pulses arrival time can be adjusted to measure the carrier lifetime. Specifically, the timing of the laser pulses is then varied and the LADA signal strength is recorded for each timing position (e.g., retarded or advanced amount), until the LADA signal has reached zero. The resulting LADA signal strength vs. time response is the plotted, as illustrated in FIG. 7C. The time taken for the LADA signal to change from maximum to minimum signal (or vice versa) corresponds to the measured laser-induced carrier lifetime. The above process is performed while repeatedly applying electrical test signal to the DUT. Laser Source

Multi-GHz repetition rate laser sources are readily available and are constructed through carefully consideration of their resonator cavity length—i.e. the shorter the oscillating cavity, the higher the repetition rate. Control over the cavity length can be manipulated and locked through the inclusion of a piezo-electric actuator located on the opposite side of an intra-cavity resonator mirror. This is the industry standard technique for repetition rate locking; however, the electronic mixer circuit required to facilitate such a scheme may differ in design and implementation. To properly incorporate the tuned-pulsed laser source into the LADA tester as described in the above embodiments, two feedback loops are required; one to control the repetition rate of the laser pulses and one to synchronize the timing of the pulses to the DUT clock. The first feedback loop, which controls the repetition rate, includes a mixer that compares the free-running repetition rate frequency of the laser to an input clock stimulus in order to produce a high-voltage driven difference signal. The difference signal is input to the piezo-electric transducer to adjust the resonator cavity length, which then adjusts the desired length so that the pulse rate matches the clock input supplied. An example of such a setup is illustrated in FIG. 6. In addition to the circuit described in FIG. 6, a secondary stabilization scheme can be included to continually monitor and correct the output voltage from the proportional-integral amplifier. This ensures that the high voltage amplifier is consistently given the correct input voltage so to provide repetition rate locking stability of a greater period of time—i.e. several days compared to tens of minutes.

Embodiments of the present invention also provide a method to extract individual timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning, or “parking”, the incident laser beam on a circuit feature of interest, then temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. The LADA measurement method further enables, simultaneously, the ability to extract flip-flop upset mapping (i.e. logic state manipulation). Traditionally, single-event upsets are mapped out by directly measuring the magnitude of laser-induced photocurrent at a particular location on the DUT. In the disclosed embodiments the method extracts the upset information while performing the LADA-based test—which introduces a new avenue for evaluating these upsets and is more efficient.

Using either single-photon absorption or, in an embodiment, two-photon absorption methodologies, the present invention stimulates p-junction and n-junction semiconductors to provide digital visualization of devices sensitive to time-related failures. Two-photon absorption enables a localized axial spatial interaction volume within which photo-currents are injected. Sampling accuracy on the order of 10 picoseconds enables specific test vector edges to be statistically displaced from a borderline pass-fail category.

LADA Waveforms

FIG. 8 illustrates an embodiment of a LADA system that enables the extraction of individual LADA waveforms per each specific (x_(i), y_(i)) location. The waveforms represent failure rate versus arrival time of the laser pulse. Such waveforms can help analyzing the behavior and/or failure mechanism of individual transistors within the DUT. The system itself incorporates many of the elements of the system of FIG. 2, and similar elements to those shown in FIG. 2 are identified with similar reference numerals, except that they are in the 8xx series.

In the system of FIG. 8, an optical element, such as a half mirror 837 directs light reflected from the DUT onto optical sensor 870. If needed, focusing lens 842 may be inserted in the path to focus the reflected light onto the optical sensor 870. Optical sensor may be, for example, a photodiode, an avalanche photodiode (APD), a photomultiplier tube, etc. In this embodiment, the optical sensor 870 is a single pixel sensor. When the LSM is operated to direct the laser pulses onto a selected location on the DUT, the light reflected from that location is sensed by the optical sensor 870, and the sensor 870 sends a corresponding intensity signal 872 to the controller 850. Consequently, for each location illuminated, a corresponding intensity signal is recorded in the controller 850. When the LSM is used to incrementally move the laser pulses to successive points, such that a given area of the DUT is successively illuminated by the laser pulses, without any further action, the resulting image from the intensity signals would be a somewhat uniform grey image, sometime referred to as salt and pepper image (utilizing a greyscale image digitalization).

In operation, a specific area of the DUT is selected for investigation and the tester is set to generate test vectors for which the devices in the selected area exhibit 50% fail rate. Then the test loop is repeated a number of times for each illuminated pixel and the intensity of the reflected light is recorded. In this respect, the term pixel refers to a spatial location which is illuminated by the laser pulses when the LSM parks the mirrors at a specific position. The intensity signal from optical sensor 870 is considered as a single pixel. However, as the LSM moves the mirrors to successive locations on the DUT to cover the entire selected area, at each position the light collected from the optical sensor is a pixel corresponding to that location. In this manner, the selected area is spatially divided into image pixels, although the optical sensor is a single pixel sensor. Conversely, the image of the sensor at each location may be represented by several pixels of the display monitor. The ratio would depend on the representation on the screen of the diameter of the sensor as imaged on the DUT. That is, the area of the DUT imaged by the sensor is referred to as one image pixel, but it may be displayed on the monitor screen by several screen pixels.

As shown in FIG. 2A, the synchronization of the laser pulses can be controlled such that the laser pulses can arrive at the DUT with controlled delay or advance with respect to the test vectors. Using this control, in one embodiment the timing electronics is configured to cause the laser to generate a train of light pulses, p, that spans the entire period of a test vector signal v, as shown in the dash-line callout of FIG. 8. Each pulse 823 in the train of pulses corresponds to a time t_(i), and the signal 872 of the light reflection collected by the optical sensor 870 at time t_(i) is recorded. This is repeated for each pixel, such that for each pixel, i.e., each illumination location (x_(i), y_(i)) within the selected area the system records intensity signals for each time t_(i). If all of the transistors within the selected area would respond identically to the test vector and laser pulses, then the resulting image is a salt and pepper noise-like image.

However, when the test vector is designed such that the transistors are at 50% failure rate, the laser pulses would push some transistors to fail at a higher rate and other transistors to pass at a higher rate. As noted by the subject inventors, the failure and pass rate of each transistor depends on the arrival time of the laser pulse with respect to the clock of the test vector. The system of FIG. 8 is configured to capture and present this information to the user. Specifically, for each pixel and pulse arrival time combination [e.g., (x_(i), y_(i), t_(i))], the test is repeated multiple time to generate a fail rate (%). We note that some transistors would be made to increase passing rate due to the laser pulses, however this can simply be recorded as failing rate below the 50% initial setup. Then, for each (x_(i), y_(i)) location, a plot can be generated to illustrate how the failing rate changes with time, t_(i). This is illustrated by the solid-line callout in FIG. 8, which illustrates a plot of failure rate versus time for selected point (x_(i), y_(i)) on the DUT.

Note that while for shorthand the plot is referred to as fail rate versus time, the reference to “time” is actually to delta time, i.e., the measure of the time difference between the test signal and the laser pulse. Thus, time t₀ may refer to a time of 10 picoseconds before the test pulse arrival, while time t₁₅ may refer to a time coincident with the test pulse leading edge and time t₅₀ may refer to time of 10 picoseconds after the trailing edge of the test pulse.

One method for arriving at a plot, such as that illustrated in the solid-line callout of FIG. 8, can be as follows. As explained above, the intensity signal is recorded for each location and time (x_(i), y_(i), t_(i)), also referred to herein as spatiotemporal volume. According to this embodiment, a two-dimensional color space is used, e.g., black and white, or grey scale, but other colors can be used. Then, for each spatiotemporal volume, if the tester indicates that the transistor failed, the pixel is recorded as a 1, e.g., white. Conversely, if the tester indicated a pass, the intensity is recorded as a 0, e.g., black. As the data is accumulated for all the pixels in the selected area of interest, pixels with devices having 50% failure rate will appear as average background color, e.g., grey. However, pixels of devices with higher than 50% failure rate will appear brighter or whiter while pixels of devices with lower failure rate will appear darker. Repeating the scanning of the display to aggregate or average the outcomes of the repeating test pattern and the charge injections would generate an image having grey background color, white pixels for mostly failing devices and dark pixels for mostly passing devices. This is illustrated in the dotted-line callout in FIG. 8.

The data used to construct the image of the dotted-line callout in FIG. 8 can also be used to construct the plots of failure rate versus time for any desired pixel, as illustrated in FIGS. 8A and 8B. Specifically, the user may select any pixel (device) and the stored modified intensity data for the selected pixel can be used to generate the plot, since the modified intensity correlates to the failure rate by the modification to 1 or 0 according to the pass/fail tester data. As shown in FIG. 8B, as the failure rate of a transistor at a specific pixel location changes, the color of that pixel changes. This correlation can be indicated by plotting the intensity signal versus time, which is in fact indicative of the failure rate over time.

As shown in FIG. 8A, the plots correlating to the white dotes or pixels indicate a higher then 50% failure rate, while plots correlating to dark dote show lower than 50% failure rate. However, the plots of FIG. 8A not just indicate the failure rate, but also indicate how the timing of the laser pulses with respect to the test clock affects the failure rate. For example, plot 8A1 indicates that the corresponding transistor tends to fail when the laser pulse arrival coincides with the leading edge of the test signal, while plot 8A2 indicates that the corresponding transistor tends to fails when the laser pulse arrival coincides with the trailing edge of the test signal. Such information can help decipher the failure mechanism of each individual transistor.

In an embodiment, functional timing diagrams can be extracted from the recorded test data to map the systematic evolution of transistor switching events. These timing diagrams may be constructed either from the application of repetitive tester loops per pixel dwell time or through the application of pseudo-random input test patterns per pixel dwell time. Accurate knowledge of both the pulse interaction time within the test loop and the resulting LADA signal strength per transistor location are required, and can be achieved with the use of short laser pulses. In an embodiment, individual timing diagrams may be extracted from synchronized single- or two-photon pulsed LADA by spatially positioning, or “parking”, the incident laser beam on a circuit feature of interest, then temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time.

Referring now to FIG. 9, an embodiment for a testing system 900 is illustrated. The system operated in conjunction with a conventional tester, e.g., Automatic Test Equipment (ATE) apparatus 905. The tester transmits stimulus vectors and clock signals to, and receives output signals from, a Device Under Test (DUT), i.e., microchip 910. The application of power, ground, input signals and transfer of results is illustrated as double-headed arrow 924. The tester is configured to repeat a sequence of test patterns and compare the results received from the DUT with expected output and provide pass or fail data through channel 926 to a Location Pass/Fail Store (accumulator) 960, which may be any standard storage/memory device. The tester is further coupled to a clock and pulse controller 920, which controls via signal channel 923 a charge carrier injector 930. The injector interacts with the Device Under Test by directing timed injection of laser pulses 928 to a small area or volume of the DUT 940. Injector 930 also collects reflections of the laser pulses from the DUT. Each location upon which the laser pulses are focused can be considered a single pixel, and the reflected light from that location can correspond to a pixel or a collection of pixels on a monitor screen 970.

As the testing progresses, a transistor which is experiencing a signal transition from low to high or high to low will simultaneously receive an injection of electron-hole pairs generated by the absorption of the photons from the laser pulses, which may potentially modify the timing characteristics of the transition. There are several ways to obtain observation of the switching transition. In an embodiment a signal 225 controls the tester which is configured to repeat a selected test pattern to obtain a ratio of 50% pass and 50% fail, prior to the injection of laser pulses. An easy to understand example for expository purposes is to start with a low clock frequency for which the device passes all vectors in the test pattern and to keep doubling the rate at which vectors are presented to the DUT until there is widespread failure. Then reduce the clock rate until those failing bits are only failing half the time. Other variables which could lead to the 50-50% mode of behavior could involve voltage. It is known how to approach this point.

By weighting pass and fail values, a simple accumulator 960 could emit a neutral value when equilibrium is obtained. In an embodiment, simply scanning the injector over the surface of the DUT will eventually result in the photons interacting with a transistor which is in transition from low to high. This will change the ratio of passes to fails and can be displayed in a map or other output format on device 970, such as a monitor. The injector is synchronized with the test pattern by providing a clock signal from the tester to the scheduler. This enables repetition of the photons injection at the same point or points of the test pattern and at time coinciding, retarded, or advanced, with respect to the test patterns. This is illustrated by the double headed arrow 922.

During the operation of the apparatus, the ATE tester repeats a test program including a test pattern and a configuration where parameters are set to obtain 50% passing results. The data is accumulated and averaged to generate a visualization of a grey field. As the injector is transited across the locations of the DUT, some locations diverge from 50% pass and the effect is that a whitish or blackish image emerges from a grey fog during time ranges of the test pattern.

The analysis or display apparatus identifies the locations of these apparitions on the die and also the time or position in the test pattern sequence when the measurements occur. The location can be correlated with a transistor on the condition that the test pattern is stimulating a signal value transition at the time the injector is actively injecting laser pulses to cause one or two photon absorption of energy sufficient to create charge carrier pairs. The method may further comprise tracing the propagation of transitions sensitive to charge carrier injection through the layout schematic of the circuit.

Additionally, the failure rate may be tracked or visualized by transforming it into a spectrum. For example, a Fourier Transform may be applied to the failure data collected for each location on the region of interest, so as to generate a spectrum for each location. The peak of the Transform would correlate to the failure rate at that particular location.

A method for data recording and analysis using the apparatus would include: configuring the tester to apply to the DUT test pattern causing transistors in the DUT to fail the tests 50% of the time without the application of laser pulses; applying the test pattern repetitively to the DUT while applying laser pulses at selected focus locations of the DUT, the laser pulses being configured to have sufficient energy to inject charge carrier pair at precise times during the test pattern; recording the tester results for each pattern repetition at each focus location, determining the locations and schedule where test results substantially diverge from 50% failure, generating a time sequence of failure rate versus time progression at locations wherein the failure rate diverge from 50% failure. To investigate the failure, the method may proceed by correlating the locations with the layout of transistors in a netlist of the design of the device under test. Additionally, a schematic annotated with the locations where the signal propagation is sensitive to charge injection can be generated. In an embodiment, the simultaneous acquisition of multiple timing diagrams may be extracted by capturing LADA activity from multiple structures within a confined region of interest in a LADA image as the laser pulse arrival time is temporally scanned with respect to the tester clock or the loop length trigger signal. Post-processing of the resulting data can then be utilized to extract the temporal evolution of transistor switching events (i.e. timing diagrams).

In an embodiment, synchronized single- or two-photon pulsed LADA-based timing diagrams may be extracted over an extrapolated physical area located across the DUT through an integrated software suite—for example, DCG Systems' NEXS (Navigation Exchange Server). This would facilitate the automatic spatiotemporal interrogation of LADA activation sites through a server-controlled CAD and circuit schematic management facility. This may be utilized in a site-by-site basis also—where individual or spatially confined LADA activations sites are probed and evaluated.

In an embodiment, this technique may be utilized to enhance the circuit descriptions of the logical path linking the LADA sites contained within the race condition. This may be utilized to construct a flat schematic representation of the logic path in a common netlist format (e.g. SPICE or Verilog). For example, by labeling the corresponding input and output blocks of a specific circuit feature accordingly.

In an embodiment, it may be desirable to extract sub-cell schematic information for guiding the “parked” laser position between associated transistors contained within the logic path. This would be beneficial for transistor-level circuit debug.

In an embodiment, the above software suite may be utilized for the analysis of two-photon-induced upset sites. This may be utilized for flip-flop transistor isolation and CAD overlay for circuit analysis and image registration, respectively.

A single event upset (SEU) is a change of state caused by charged particles such as ions, electrons, etc, or electro-magnetic radiation striking a sensitive node in a micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (e.g. memory “bit”). The error in device output or operation caused as a result of the strike is called an SEU or a soft error. Another aspect of the invention is acquiring absorption-induced upset sites. The feedback circuit in a flip-flop is easier to disturb than static combinational logic gates. In a scan test, the flip-flops are exercised almost every test cycle. A single laser-induced disturbance during any test cycle causes the test to fail. However, this tester fail is different than the engineered race condition fail for LADA. During functional testing or operation, most flip-flops are not exercised every cycle. Upset sites have an opportunity for disturbance following each laser pulse during the test. Therefore, an initially low probability of disturbance becomes almost 100% cumulative probability with 1000+ opportunities per test (assuming a 100 MHz laser repetition rate). Hence, the observation of intense, yet non-destructive, upset sites. Note here that upset sites can be removed simply by modifying the test. The disclosed methodology also provides realization of non-destructive, two-photon-absorption-induced upset sites acquired through a LADA-based implementation scheme. This methodology offers a novel alternative to single-event upset execution and evaluation.

With the single or two photon LADA testing described above, the laser pulses are designed so as to shift the switching time of the transistor illuminated by the pulses. That is, the laser pulses retard or advance the timing of the transistor switching, thus causing it to pass or fail the test—which generally probes to see whether the transistor switched at the time it was supposed to do so. However, it has also noted that the pulses can have sufficient energy so as to alter or upset the state of an individual memory unit. For example, if a flip-flop is set to store a “0”, the arrival of a laser pulse with sufficient peak energy can cause the flip-flop to change state into the opposite state, i.e., into a “1” without damaging the device. This reversal can be detected by the ATE and reported for each location illuminated by the laser pulses. Thus, using the techniques described herein, especially using a 2pLADA, one can easily detect memory cells that are prone to single-event upsets.

With the LADA testing noted above, a train of laser pulses would include one pulse that is timed to cause the transistor to pass or fail the test. The remaining pulses in the train do not contribute to the test. Conversely, for single-event upset testing, every pulse in the train can cause the memory cell to flip to the opposite state. Thus, using a train of short pulses at high peak power is an efficient method to study single-event upsets. The more pulses in the train of a test loop, the higher the probability that the cell will flip.

Some of the embodiments and pulsed laser source discussions above make reference to a MLL based system. However, in some embodiments a “non-oscillator” based laser pulse system can be used, as long as it has pulse width and jitter performance allowing for temporal resolution to acquire the waveforms. Furthermore, this non oscillator embodiment can be synchronized by stimulating the firing of the pulses directly with a trigger from the tester or from a controllable delayed trigger originating from the tester. In either case, femtosecond laser pulses are the preferred stimulus for efficient 2pLADA generation, although picosecond pulses may also be utilized—at the expense of reduced two-photon absorption (TPA) efficiency (i.e. SNR) and increased invasiveness. The wavelength range captured for 2pLADA should be 1250 nm-1550 nm—with 1250 nm offering the best performance in terms of efficiency and resolution. Conversely, nanosecond to femtosecond laser pulses can be used for single-photon LADA; with an obvious link between laser pulse duration and temporal resolutions gain, spatial resolution gain, invasiveness, and delivered peak power. The wavelength of choice for single-photon LADA should be 1064 nm.

It should be understood that processes and techniques described herein are not inherently related to any particular apparatus and may be implemented by any suitable combination of components. Further, various types of general purpose devices may be used in accordance with the teachings described herein. It may also prove advantageous to construct specialized apparatus to perform the method steps described herein.

While this invention has been discussed in terms of exemplary embodiments of specific materials, and specific steps, it should be understood by those skilled in the art that variations of these specific examples may be made and/or used and that such structures and methods will follow from the understanding imparted by the practices described and illustrated as well as the discussions of operations as to facilitate modifications that may be made without departing from the scope of the invention defined by the appended claims. 

1. A laser assisted device alteration (LADA) system operable in conjunction with a testing equipment (TE) for testing integrated circuit device under test (DUT), comprising: a controller configured to operate the timing electronics for timing the laser pulses to arrive at transistors in the DUT at times synchronized to the clock time and enable incorporating a delay or advance of the laser pulses with respect to the clock time, to thereby alter the transistors electrical response to test signals applied to the DUT from the TE, the controller being further configured to detect the altered transistors electrical response, receive the corresponding intensity signals, and utilize the electrical response and intensity signals to produce a plot of electrical response versus time for a selected location on the DUT; and a single-pixel sensor detecting reflections of the laser pulses from the DUT and generating corresponding intensity signals.
 2. The system of claim 1, wherein the plot of electrical response versus time corresponds to the synchronization of laser pulses to the clock signal.
 3. The system of claim 1, wherein the plot of electrical response versus time comprises a plot of failure rate versus arrival time of the laser pulses relating to test signals of the TE.
 4. The system of claim 1, wherein the pulse rate of the laser pulses is configured as a multiple of the clock signal.
 5. The system of claim 1, wherein the optical arrangement directs the laser pulses onto desired locations by successively directing a train of laser pulses to each desired location to thereby illuminate a selected area of the DUT.
 6. The system of claim 1, wherein the pulsed laser source generates a beam of laser pulses and wherein the optical arrangement directs the laser pulses onto desired locations by successively parking the laser beam at each desired location.
 7. The system of claim 1, wherein the controller utilizes the electrical response and intensity signals by detecting a test failure or pass at each desired location, and when detecting a failure setting the intensity signal to a first color and when detecting a pass setting the intensity signal to a second color.
 8. The system of claim 7, wherein the first color is one of black and white and the second color is the other of black and white.
 9. The system of claim 1, wherein the controller further applied a Fourier Transform to the plot of electrical response versus time.
 10. The system of claim 1, further comprising a monitor, and wherein the controller displays on the monitor an image of an area of interest, wherein locations having transistors failing at above 50% rate are displayed as one color and locations having transistors failing at below 50% rate are displayed as second color; the controller further displaying on the monitor the plot of electrical response versus time for each selected one of the locations having transistors failing at above 50% rate and locations having transistors failing at below 50% rate.
 11. A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising: generating a laser beam comprising a train of laser pulses; sequentially positioning the laser beam on each pixel location within an area of interest of the DUT and performing a test loop at each pixel location, wherein the test loop comprises temporally scanning arrival time of the laser pulses with respect to the clock signal while the ATE applies the test signal to the DUT and for each spatiotemporal volume recording a pass/fail result of the DUT, wherein spatiotemporal volume is defined as a combination of a spatial coordinate on the DUT and arrival time of a laser pulse; and, generating a plot of failure rate versus time for a plurality of pixel locations for which pass/fail results indicate a failure rate deviating from a predetermined value.
 12. The method of claim 11, wherein the laser pulses are configured to have wavelength and duration calculated to cause two-photon absorption within the DUT.
 13. The method of claim 11, wherein the laser pulses are configured to have wavelength and duration calculated to cause single-photon absorption within the DUT.
 14. The method of claim 11, wherein recording a pass/fail result of the DUT further comprises recording a first color when the DUT pass and recording a second color when the DUT fails.
 15. The method of claim 14, further comprising generating an image on a monitor using the first and second colors.
 16. The method of claim 14, wherein generating the plot of failure rate versus time comprises selecting a spatial coordinate on the DUT and plotting the first and second color versus time.
 17. The method of claim 16, wherein the first color is one of black and white and the second color is the other of black and white.
 18. The method of claim 11, wherein the pixel location includes a flip-flop, and wherein the train of laser pulses is configured to generate a single-upset event in the flip-flop.
 19. The method of claim 11, further comprising correlating plurality of pixel locations for which pass/fail results indicate a failure rate deviating from 50% with layout of transistors in a netlist.
 20. A method using laser assisted device alteration (LADA) for testing an integrated device under test (DUT) that is coupled to a testing equipment (TE) the TE generating a clock signal and a test signal, the method comprising: configuring the TE to apply to the DUT test pattern causing transistors in the DUT to fail at least one of the tests without the application of laser pulses; applying the test pattern repetitively to the DUT while applying laser pulses at selected focus locations of the DUT, the laser pulses being configured to have sufficient energy to inject charge carrier pair at precise times during the test pattern; recording the tester results for each test pattern repetition at each focus location; determining locations where test results substantially diverge from 50% failure; generating a sequence of failure rate versus time progression at locations wherein the failure rate substantially diverges. 